1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a circuit configuration of a redundancy determination circuit for replacing a defective memory cell with a redundant memory cell.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) used as a main memory, though having been progressed in its high speed operation, still cannot follow an operating speed of a microprocessor (MPU). Therefore, a fear exists that an access time and a cycle time of a DRAM act as bottle necks against performance of the system as a whole to reduce it. In recent years, a proposal has been made, in light of such a situation, of a double data rate SDRAM (hereinafter referred to as DDR-SDRAM) operating in synchronization with a complementary clock signal as a main memory for a high speed MPU.
In DDR-SDRAM, for the purpose of a high speed access, specifications are common that get a high speed access to consecutive bits in synchronization with a rise and fall of a clock signal.
A double data rate scheme commonly employs a configuration in which a memory array is divided into two memory blocks: a memory block having even-numbered bit lines corresponding to even-numbered addresses and a memory block having odd-numbered bit lines corresponding to odd-numbered addresses, wherein an even-numbered bit line and an odd-numbered bit line are selected in parallel to each other to get simultaneous accesses, thereby facilitating a data output operation at a double clock frequency. In such a configuration, there has generally been used a method in which an address inputted externally is converted to even-numbered and odd-numbered addresses.
FIG. 7 is a schematic block diagram showing an overall configuration of a conventional synchronous semiconductor memory device 10.
Referring to FIG. 7, a synchronous semiconductor memory device 10 includes: a memory block 6a corresponding to even-numbered addresses and a memory block 6b corresponding to odd-numbered addresses, which are obtained by dividing a memory array into the two blocks. Memory blocks 6a and 6b each have memory cells arranged in a matrix and redundant memory cells for saving a defective memory cell. Here, typically shown in memory block 6a are one word line WL provided correspondingly to a row, one even-numbered bit line BLE provided correspondingly to a column and one redundant bit line BLSE provided corresponding to a redundant memory cell column constituted of redundant memory cells. In addition, typically shown in memory block 6b are one word line WL provided correspondingly to a row, one odd-numbered bit line BLO provided correspondingly to a column and one redundant bit line BLSO provided corresponding to a redundant memory cell column constituted of redundant memory cells. Hereinafter, the redundant bit lines are simply referred to as redundant bit line BLS in a collective manner.
Note that in the following examples, memory blocks 6a and 6b each have 256 bit lines and a plurality of bit lines, which is one example. Furthermore, in memory block 6a, even-numbered addresses are sequentially allocated to even-numbered bit lines. For example, addresses 0#, 2#, 4#, . . . and so on are sequentially allocated. Furthermore, in memory block 6b, odd-numbered addresses are sequentially allocated to odd-numbered bit lines. For example, addresses 1#, 3#,5#, . . . and so on are sequentially allocated.
Synchronous semiconductor memory device 10 further includes: a control signal generating circuit 20 generating control signals for internal circuits and control signal generating circuit 20 especially generates an internal clock signal CLK (hereinafter also simply referred to as clock signal CLK) used in timing control of internal circuits in synchronization with an external clock signal Ext.CLK.
Synchronous semiconductor memory device 10 further includes: a now decoder 2 performing row selection in memory blocks 6a and 6b; column decoders 3a and 3b receiving, as respective inputs, even-numbered and odd-numbered addresses to perform column selection; spare column decoders 4a and 4b performing column selection for redundant bit lines BLS in respective memory blocks according to a defect determination signal; a multiplexer 5a outputting read data read out from memory block 6a to an amplifier 7a on the basis of a column select operation by one of column decoder 3a and spare column decoder 4a; and a multiplexer 5b outputting read data read out from memory block 6b to an amplifier 7b on the basis of a column select operation by one of column decoder 3b and a spare column decoder 4b. 
Synchronous semiconductor memory device 10 further includes: amplifiers 7a and 7b amplifying read data outputted from multiplexers 5a and 5b; a parallel-serial conversion circuit 8 sequentially arranging two read data amplified by amplifiers 7a and 7b so as to output the two data in synchronization with a rise and fall, respectively, of clock signal CLK; and an output buffer 9 outputting read data arranged by parallel-serial conversion circuit 8 to an external terminal DQ.
Synchronous semiconductor memory device 10 further includes: a redundancy determination circuit 35a for determining redundancy of memory block 6a corresponding to an even-numbered address; and a redundancy determination circuit 35b for determining redundancy of memory block 6b corresponding to an odd-numbered address. Redundancy determination circuits 35a and 35b include respectively: program circuits 33a and 33b (hereinafter also referred to as program circuit 33 in a collective manner) setting column addresses of defective memory cells (hereinafter also referred to as defect address); and comparison circuits 32a and 32b (hereinafter also referred to as comparison circuit 32 in a collective manner) comparing a defective address and an inputted address with each other to generate defect determination signals SCEE and SCEO on the basis of results of the comparisons.
Synchronous semiconductor memory device 10 further includes: an address buffer 30 buffering a column address CA inputted from an external address terminal PINA to output addresses to column decoders 3a and 3b. Address buffer 30 has a burst counter 31. Burst counter 31 counts up a bit or bits of part of a column address on the basis of a preset burst length in synchronization with clock signal CLK. Address buffer 30, on burst reading, latches residual bits obtained after excluding the bit or bits of part of the column address and outputs the residual bits together with the bit or bits of part which have been counted up. Herein, the burst length indicates a length of data outputted consecutively.
Synchronous semiconductor memory device 10 includes an even-numbered address buffer 40, provided between address buffer 30 and column decoder 3a, and generating an even-numbered address CAE for performing a column select operation in memory block 6a and even-numbered address buffer 40 receives, as an input, a column address CA including the bit or bits of part, which have been counted up by a burst counter 31 of address buffer 30. Synchronous semiconductor memory device 10 further includes: an odd-numbered address buffer 50, provided between address buffer 30 and column decoder 3b, and generating an odd-numbered address CAO for performing a column select operation in memory block 6b and odd-numbered address buffer 50 receives, as an input, a column address CA including the bit or bits of the part, which have been counted up by burst counter 31 of address buffer 30.
Address buffer 30 receives column address CA  less than 8:0 greater than  from external address terminal PINA. Note that column address CA  less than 8:0 greater than  is indicated column addresses CA less than 0 greater than  to CA less than 8 greater than . Similarly, a symbol  less than x:0 greater than  is hereinafter used in collective expression of a sequence of  less than 0 greater than  to  less than x greater than . Alternatively, column addresses CA less than 0 greater than  to CA less than x greater than  are also collectively referred to as column address CA.
Description, here, will be given of burst reading of synchronous semiconductor memory device 10.
Column decoders 3a and 3b select groups of bit lines on which burst reading is performed in respective memory blocks 6a and 6b according to column address CA of an upper bit or bits defined according to a burst length. For example, when a burst length is 2, one even-numbered line and one odd-numbered bit line are selected. When a burst length is 4, two even-numbered bit lines and two odd-numbered bit lines are selected.
Similarly, when a burst length is 8, four even-numbered bit lines and four odd-numbered bit lines are selected.
For thus selected bit line or lines corresponding to a burst length, designation is performed of an address in the leading place (hereinafter also referred to as a start address) at which data is firstly read out according to column address of a lower bit or bits, followed by designations of an address in the next place in ascending order. That is, when a start address is an even-numbered address, an odd-numbered address in the next place is designated in ascending order, thus selecting both addresses in parallel to each other.
Then, column address CA of a lower bit or bits is counted up by burst counter 31 according to a burst length, followed by designation of the next start address. With repetitions of the operation, burst reading corresponding to a burst length is performed. Burst reading is disclosed in technical literatures such as Samsung electronics DDR SDRAM Specification Version 0.6, REV. 0.6 Mar. 21, 2001.
FIG. 8 is a timing chart in a case of a burst length 4. Here is shown a case where addresses 0# to 3# are selected according to upper bits of column address CA.
For example, a start address is designated on the basis of column address CA inputted from an external address terminal together with a read instruction at time point t1.
When a start address is 0#, bit lines with addresses 0# and 1# are both selected, followed by selection of bit lines with addresses 2# and 3# in the next run.
Parallel selection is performed of even-numbered and odd-numbered bit lines corresponding to start address 0# and address 1# according to column address CA from outside in synchronization with a rise of clock signal at time point t1. In response to this, read data is outputted to parallel-serial conversion circuit 8. The next start address is designated as address 2# by counting-up of burst counter 31 in synchronization with a fall of clock signal at time point t2 and address 3# is also designated in ascending order. Parallel selection is performed of even-numbered and odd-numbered bit lines corresponding to start address 2# and address 3# in synchronization with a rise of clock signal at time point t3. In response to this, read data is outputted to parallel-serial conversion circuit 8.
Parallel-serial conversion circuit 8 arranges and outputs read data in response to a rise and fall of clock signal starting at time point t4, and read data on bit lines corresponding to addresses 0#, 1#, 2# and 3# in ascending order starting with a start address 0# in the first time of the runs are sequentially outputted from output buffer 9.
Similarly, in a case where a start address is 1#, bit lines with addresses 1# and 2# are both selected, followed by selection of both of bit lines with addresses 3# and 0#. In company with this, read data on bit lines corresponding to addresses 1#, 2#, 3# and 0# in ascending order starting with start address 1# in the first time of the runs are sequentially outputted from output buffer 9.
Similarly, in a case where a start address is 2#, bit lines with addresses 2# and 3# are both selected, followed by selection of both of bit lines with addresses 0# and 1#. In company with this, read data on bit lines corresponding to addresses 2#, 3#, 0# and 1# in ascending order starting with start address 2# in the first time of the runs are sequentially outputted from output buffer 9.
Similarly, in a case where a start address is 3#, bit lines with addresses 3# and 0# are both selected, followed by selection of both of bit lines with addresses 1# and 2#. In company with this, read data on bit lines corresponding to addresses 3#, 0#, 1# and 2# in ascending order starting with start address 3# in the first time of the runs are sequentially outputted from output buffer 9.
FIG. 9 is a table showing a relationship of a start address designated according to an input of column address CA of a lower bit, and even-numbered address CAE  less than 0 greater than  and odd-numbered address CAO  less than 0 greater than  given to respective column decoders 3a and 3b when the start address is designated in such a way. The table shown in FIG. 9 is corresponding to a case of burst length 2. Here, addresses 0# and 1# are selected according to column address CA of an upper bit. Furthermore, when column address CA  less than 0 greater than  of a lower bit is 0, address 0# is selected, and when column address is 1, address 1# is selected. As one example, when column address CA  less than 0 greater than  is 0, start address is designated as 0#. The next address 1# is designated similarly in ascending order. Therefore, when start address 0# is designated, even-number address CAE  less than 0 greater than  of a lower bit given to column decoder 3a is 0. Furthermore, odd-numbered address CAO  less than 0 greater than  of a lower bit given to column decoder 3a is 1.
In company with this, data is read out from bit lines corresponding to addresses 0# and 1# in parallel to each other. The order for outputting data is such that read data is outputted from output buffer circuit 9 in the order of addresses 0# and 1#.
FIG. 10 is a table showing a relationship of a start address designated according to an input of column address CA  less than 1:0 greater than  of lower bits, and even-numbered address CAE  less than 1:0 greater than  and odd-numbered address CAO  less than 1:0 greater than  given to respective column decoders 3a and 3b when the start address is designated in such a way. The table shown in FIG. 10 is corresponding to a case of burst length 4. Here, addresses 0# to 3# are selected according to column address CA of upper bits.
Furthermore, addresses 0# to 3# are selected correspondingly to values of column address CA  less than 1:0 greater than . To be concrete, start address 0# is designated in correspondence to xe2x80x9c00xe2x80x9d from an upper bit side of column address CA  less than 1:0 greater than . Start address 1# is designated in correspondence to xe2x80x9c01xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than . Start address 2# is designated in correspondence to xe2x80x9c10xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than . Start address 3# is designated in correspondence to xe2x80x9c11xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than .
As one example, when xe2x80x9c00xe2x80x9d is inputted from the upper bit side of column address CA  less than 1:0 greater than , a start address in the leading place is designated as 0#. With such designation, even-number address CAE  less than 1:0 greater than  given to column decoder 3a assumes xe2x80x9c00xe2x80x9d from the upper bit side in correspondence to address 0#. Odd-numbered address CAO  less than 1:0 greater than  given to column decoder 3b assumes xe2x80x9c01xe2x80x9d from the upper bit side in correspondence to address 1#. In company with this, parallel selection is performed of an even-numbered bit line and an odd-numbered bit line corresponding to respective addresses 0# and 1#. Read data is arranged in and outputted from parallel-serial conversion circuit 8 in the order of bit lines corresponding to respective addresses 0# and 1#. Then, burst counter 31 counts up column address of the lower bits in synchronization with clock signal CLK to increment a value of column address CA  less than 1:0 greater than  by 2. Here, a value xe2x80x9c00xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than  is counted up to xe2x80x9c10xe2x80x9d. That is, start address 0# is changed to 2#. Then, even-numbered address CAE  less than 1:0 greater than  corresponding to address 2# given to column decoder 3a assumes xe2x80x9c10xe2x80x9d from the upper bit side. Furthermore, odd-numbered address CAO  less than 1:0 greater than  corresponding to address 3# given to column decoder 3b assumes xe2x80x9c11xe2x80x9d from the upper bit side. In company with this, parallel selection is performed of bit lines corresponding to addresses 2# and 3#. Read data is arranged in and outputted from parallel-serial conversion circuit 8 in the order of bit lines corresponding to respective addresses 2# and 3#. Burst counter 31, in a case of a burst length 4, counts up values of the lower 2 bits on counting-up without a carry-over.
FIG. 11 is a table showing a relationship of a start address designated according to an input of column address CA  less than 2:0 greater than  of lower bits, and even-numbered address CAE  less than 2:0 greater than  and odd-numbered address CAO  less than 2:0 greater than  given to respective column decoders 3a and 3b when the start address is designated in such a way. The table shown in FIG. 11 is corresponding to a case of burst length 8. Here, addresses 0# to 7# are selected according to column address CA of the upper bits.
Furthermore, addresses 0# to 7# are selected in correspondence to respective values of column addresses CA  less than 2:0 greater than . To be concrete, start address 0# is designated in correspondence to xe2x80x9c000xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 1# is designated in correspondence to xe2x80x9c001xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 2# is designated in correspondence to xe2x80x9c010xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 3# is designated in correspondence to xe2x80x9c011xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 4# is designated in correspondence to xe2x80x9c100xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 5# is designated in correspondence to xe2x80x9c101xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 6# is designated in correspondence to xe2x80x9c110xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than . Start address 7# is designated in correspondence to xe2x80x9c111xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than .
When xe2x80x9c000xe2x80x9d is inputted from the upper bit side of column address CA  less than 2:0 greater than , a start address in the leading place is set to 0#. In response to this, xe2x80x9c000xe2x80x9d corresponding to address 0# and xe2x80x9c001xe2x80x9d corresponding to address 1# are therefore given to respective column decoders 3a and 3b. 
Burst counter 31 then counts up to add 2 to a value of column address CA  less than 2:0 greater than  in synchronism with clock signal CLK. A value of xe2x80x9c000xe2x80x9d from the upper bit side of column address CA  less than 2:0 greater than  is counted up to xe2x80x9c010xe2x80x9d. That is, start address 0# in the leading place is changed to 2#. In response to this, xe2x80x9c010xe2x80x9d corresponding to address 2# and xe2x80x9c011xe2x80x9d corresponding to address 3# are therefore given to respective column decoders 3a and 3b. 
Burst counter 31 then counts up in synchronism with clock signal CLK to increase column address CA  less than 2:0 greater than  to xe2x80x9c110xe2x80x9d from the upper bit side. That is, start address 2# in the leading place is changed to 4#. In response to this, xe2x80x9c100xe2x80x9d corresponding to address 4# and xe2x80x9c101xe2x80x9d corresponding to address 5# are therefore given to respective column decoders 3a and 3b. 
Burst counter 31 then counts up in synchronism with clock signal CLK to increase column address CA  less than 2:0 greater than  to xe2x80x9c110xe2x80x9d from the upper bit side. That is, start address 4# in the leading place is changed to 6#. In response to this, xe2x80x9c110xe2x80x9d corresponding to address 6# and xe2x80x9c111xe2x80x9d corresponding to address 7# are therefore given to respective column decoders 3a and 3b. 
In company with this, data of a burst length 8 from bit lines corresponding to start addresses 0#, 1#, . . . 7# is sequentially arranged in and outputted from parallel-serial conversion circuit 8. Note that, burst counter 31, in a case of a burst length 8, counts up lower three bits on counting-up without a carry-over.
Considered here is about even-numbered address CAE and odd-numbered address CAO inputted to column decoders 3a and 3b on the basis of an input of column address CA.
Column address CA  less than 0 greater than  corresponds to an address indicating one of even-numbered and odd-numbered addresses. When column address CA  less than 0 greater than  is 0, it is an even-numbered address, while when column address CA  less than 0 greater than  is 1, it corresponds to an odd-numbered address. Therefore, even-numbered address CAE  less than 0 greater than  and odd-numbered address CAO  less than 0 greater than  are only to simply express, for the sake of convenience, that those are even-numbered address and an odd numbered address; an even-numbered address CAE  less than 0 greater than  is fixed to 0 as a value and an odd-numbered address CAO  less than 0 greater than  is fixed to 1 as a value.
Therefore, effective even-numbered address CAE  less than 8:1 greater than  other than even-numbered address CAE  less than 0 greater than  is inputted to column decoder 3a. Furthermore, effective odd-numbered address CAO  less than 8:1 greater than  other than even-numbered address CAO  less than 0 greater than  is inputted to column decoder 3b. 
Then, in a case of a burst length 4 of FIG. 10, for example, if a start address even-numbered in counting starting with the leading place is 0# as selected according to an input of xe2x80x9c00xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than , a necessity arises for selecting the next address 1# in ascending order. That is, it is required to give xe2x80x9c00xe2x80x9d and xe2x80x9c01xe2x80x9d to respective column addresses 3a and 3b from the upper bit side. Then, inputted column address CA  less than 1:0 greater than  as is can be used for even-numbered address CAE without conversion in any way. Odd-numbered address CAO can be used as is since, though odd-numbered address CAO assumes a value obtained by adding 1 to column address CA  less than 1:0 greater than , odd-numbered address CAO  less than 0 greater than  is fixed to 1; therefore no necessity arises for converting column address CA  less than 1:0 greater than .
However, for example, in a case where start address 1# odd-numbered starting with the leading place in correspondence to inputting of xe2x80x9c01xe2x80x9d from the upper bit side of column address CA  less than 1:0 greater than , a necessity arises for giving xe2x80x9c10xe2x80x9d and xe2x80x9c01xe2x80x9d from the upper bit side to respective column decoders 3a and 3b since it is required that the next address 2# is selected in ascending order. In this case, inputted column address CA  less than 1:0 greater than  can be used as odd-numbered address CAO as is. Even numbered address CAE assumes a value obtained by adding 1 to inputted column address CA  less than 1:0 greater than , thereby requiring a carry-over. In this case, it is required that column address CA  less than 1 greater than  is converted to generate effective even-numbered address CAE  less than 1 greater than .
That is, in a case where a start address in an even-numbered place of the order is selected in correspondence to column address CA  less than 1:0 greater than , an odd-numbered address selecting an address in an odd numbered place is not necessary to be converted since the lowest bits CAE  less than 0 greater than  and CAO  less than 0 greater than  of an even-numbered address and an odd-numbered address, respectively, are fixed, though a value of CA  less than 0 greater than , which is the lowest bit of column address CA, assumes 1. On the other hand, in a case where a start address in an odd-numbered place of the order is selected in correspondence to column address CA  less than 1:0 greater than , an even-numbered address selecting an address in an even numbered place requires conversion of column address CA  less than 1 greater than  to even-numbered address CAE  less than 1 greater than  used for a column select operation since even-numbered address CAE assumes a value with a carryover due to adding 1 to column address CA  less than 1:0 greater than .
In a case of a burst length 8 of FIG. 11 as well, similar to the case of a burst length 4 of FIG. 10, if a start address is selected in correspondence to column address CA  less than 2:0 greater than  of lower bits, a necessity arise for a conversion operation when a carry-over occurs in selection of the next address.
To be concrete, in a case where, similar to the case of a burst length 4, a start address in an odd-numbered place is selected in correspondence to column address CA  less than 2:0 greater than , an odd-numbered address selecting an address in an even-numbered place requires conversion of column address CA  less than 1 greater than  to even-numbered CAE  less than 1 greater than  since a carry-over occurs due to adding 1 to column address CA  less than 2:0 greater than .
For example, in a case where column address CA  less than 2:0 greater than  is inputted from the upper bit side with xe2x80x9c011xe2x80x9d to select a start address 3# odd-numbered in counting starting with the leading place, xe2x80x9c100xe2x80x9d and xe2x80x9c011xe2x80x9d are necessary to be given from the upper bit side to respective column decoders 3a and 3b since it is required that the next start address 4# is selected in ascending order. In this case, inputted column address CA  less than 2:0 greater than  has only to be used as is as odd-numbered address CAO. However, even-number address. CAE requires conversion of column address CA  less than 2 greater than  to effective even-address CAE  less than 2 greater than  since a carry-over is required by adding 1 to inputted column address CA  less than 2:0 greater than . For example, in a case where column address CA  less than 2:0 greater than  is inputted with xe2x80x9c111xe2x80x9d from the upper bit side to select start address 7# odd-numbered in counting staring with the leading place as well, effective even-number CAE  less than 2 greater than  has to be obtained from conversion of column address CA  less than 2 greater than .
Therefore, while odd-numbered address CAO can be used as is without conversion of column address CA, even-numbered address CAE requires conversion of column address CA in a prescribed condition.
FIGS. 12 and 13 are diagrams of configuration of decoders DC1 and DC2 converting even-numbered address CAE  less than 1 greater than  and even-numbered address CAE  less than 2 greater than  included in even-number address buffer 40 in a prescribed condition.
Referring to FIG. 12, decoder DC1 includes NOR circuits 41 to 43; a NAND circuit 44; an OR circuit; and inverters 46 to 48.
NOR circuit 41 outputs a result of a NOR logical operation according to inputs of burst control signals MBL4 and MBL8 through inverter 46 to NAND circuit 44. NAND circuit 44 transmits a result of a NAND logical operation according to an output signal from inverter 46 and, as an input, column address CA  less than 0 greater than  to a node NO. NOR circuit 43 receives column address CA  less than 1 greater than  and an input, which is an output signal of NAND circuit 44 transmitted to node NO to output a result of a NOR logical operation to OR circuit 45. NOR circuit 42 receives, as inputs, an inverted signal of a signal transmitted to node NO through inverter 47 and an inverted signal of column address CA  less than 1 greater than  through inverter 48 to output a result of a NOR logical operation to OR circuit 45. OR circuit 45 receives inputs from NOR circuits 42 ad 43 to output a result of an OR operation as even-address CAE  less than 1 greater than . Note that burst control signals MBL2 and MBL4 are inputted on the basis of a set burst length. Here, burst control signal MBL4 is a signal indicating that a burst length is 4. Burst control signal MBL8 is a signal indicating that a burst length is 8.
Decoder DC1 converts column address CA  less than 1 greater than  to generate even-numbered address CAE  less than 1 greater than  if column address CA is in a prescribed condition in a case of a burst length 4 or 8. The prescribed condition is a case where, when inputted column address CA is added with 1, a carry-over of column address CA  less than 0 greater than  is required, that is a case where column address CA  less than 0 greater than  is 1.
To be concrete, when column address CA  less than 1:0 greater than  is xe2x80x9c01xe2x80x9d or xe2x80x9c11xe2x80x9d from the upper bit side, the next column address CA is accompanied with a carry-over. In the cases, even-numbered address CAE  less than 1 greater than  is converted to inverted data of column address CA  less than 1 greater than .
FIG. 13 shows decoder DC2 outputting even-numbered address CAE  less than 2 greater than .
Referring to FIG. 13, decoder DC2 includes: a NAND circuit 49 receiving inputs of burst control signal MBL8 and column address CA  less than 1:0 greater than  to transmit a result of a NAND logical operation to a node N1; a NOR circuit 53 outputting a result of a NOR logical operation on column address CA  less than 2 greater than  and a signal transmitted to node N1 to OR circuit 54; a NOR circuit 52 receiving, as inputs, an inverted signal of a signal transmitted to node N1 through inverter 50 and an inverted signal of column address CA  less than 2 greater than  through inverter 51 to output a result of a NOR logical operation result; and an OR circuit 54 receiving inputs from NOR circuits 52 and 53 to output a result of an OR logical operation as even-numbered address CAE  less than 2 greater than .
Decoder DC2 converts column address CA  less than 2 greater than  to generate even-numbered address CAE  less than 2 greater than  if column address CA is in a prescribed condition in a case of a burst length 8. The prescribed condition is a case where, when inputted column address CA is added with 1, a carry-over of column address CA  less than 1 greater than  is required, that is a case where column address CA  less than 1:0 greater than  is xe2x80x9c11xe2x80x9d from the upper bit side.
To be concrete, when column address CA  less than 2:0 greater than  is xe2x80x9c011xe2x80x9d or xe2x80x9c111xe2x80x9d from the upper bit side, the next column address CA is accompanied with a carry-over. In the cases, even-numbered address CAE  less than 2 greater than  is converted to inverted data of column address CA  less than 2 greater than .
Column address CA is converted using decoders DC1 and DC2 in the prescribed condition to thereby, be able to select a desired address. Accordingly, parallel selection can be performed of two bit lines corresponding to an even-numbered address and an odd numbered address; therefore a high speed double data rate scheme can be realized.
On the other hand, in a case where a defective memory cell is included in memory cells, redundant memory cells are provided in order to save such a defective memory cell and, when a column address selecting a defective memory cell is inputted, a redundant bit line corresponding to a redundant memory cell is selected instead of a bit line corresponding to a defective cell. A redundancy determining circuits 35a and 35b performs a redundancy determination on whether or not a defective memory cell has been selected.
FIG. 14 is a circuit diagram of a program unit PU setting a defect. address of one bit included in a program circuit in each of redundancy determining circuits 35a and 35b. 
Program unit PU includes a P-channel MOS transistor 82; an N-channel MOS transistor 83; inverters 80 and 81; and a fuse element 84. P-channel MOS transistor 82 is connected between power supply voltage VCC and node N10 and receives a control signal xcfx861 to turn itself on/off. N-channel MOS transistor 83 is connected between node N10 and fuse element 84 and receives, as an input, a control signal xcfx862 to turn itself on/off. Fuse element 84 is placed between N-channel MOS transistor 83 and substrate voltage VSS and can be blown by irradiation with laser light from outside in a non-volatile manner. Inverter 80 inverts a signal transmitted to node N10 to transmit the inverted signal to a node 11 and inverter 81 inverts a signal transmitted to node N11 to transmit the inverted signal to node N1. A latch is constituted of inverters 80 and 81. A signal transmitted to node N11 is outputted to a comparison circuit 32 as a defect address FCA of one bit. For example, if control signal xcfx861 is at L level for a prescribed period, defect address FCA of one bit is reset to 0. If control signal xcfx862 is at H level for a prescribed period, defect address FCA of one bit is 1 in a case where fuse element 84 is not blown. On the other hand, if fuse element 84 has been blown, defect address FCA of one bit stays at 0 as is. Therefore, by blowing fuse element 84, defect address FCA of one bit can be set to 0 through programming.
Therefore, a plurality of program units PU are arranged in parallel to each other and programming is performed in each of plurality of program units PU, thereby enabling setting of defect address FCA corresponding to a column address of a defective memory cell.
FIG. 15 is a circuit configuration diagram of comparison circuit 32a. 
Comparison circuits 32a and 33b are of the same circuit configuration as each other and description here will be given of comparison circuit 32a. 
Comparison circuit 32a includes: exclusive NOR circuits 60 to 67; NAND circuits 68 to 71 and 74; NOR circuits 72 and 73; and an inverter 75. Exclusive NOR circuit 60 receives, as inputs, even-numbered address CAE  less than 1 greater than  and defect address FCA  less than 1 greater than  to output a result of an exclusive NOR logical operation. The other exclusive NOR circuits 61 to 67, in a similar manner, receive even-numbered addresses CAE  less than 2 greater than  to CAE  less than 8 greater than  and defect addresses FCA  less than 2 greater than  to FCA  less than 8 greater than  of bits corresponding to respective even-numbered address CAE  less than 2 greater than  to CAE  less than 8 greater than  to output results of exclusive NOR logical operations. NAND circuit 68 receives inputs from exclusive NOR circuits 60 and 61 to output a result of a NAND logical operation to NOR circuit 72. NAND circuit 69 receives inputs from exclusive NOR circuits 62 and 63 to output a result of a NAND logical operation to NOR circuit 72. NAND circuit 70 receives inputs from exclusive NOR circuits 64 and 65 to output a result of a NAND logical operation to NOR circuit 73. NAND circuit 71 receives inputs from exclusive NOR circuits 66 and 67 to output a result of a NAND logical operation to NOR circuit 73. NAND circuit 72 receives inputs from NAND circuits 68 and 69 to output a result of a NOR logical operation to NAND circuit 74. NAND circuit 73 receives, as inputs, outputs of NAND circuits 70 and 71 to output a result of a NOR logical operation to NAND circuit 74. NAND circuit 74 receives inputs from NOR circuits 72 and 73 to output a result of a NAND logical operation to inverter 75. Inverter 75 outputs an inverted signal of an output signal of NAND circuit 74 as defect determination signal SCE.
Comparison circuit 32a compares even-numbered address CAE  less than 8:1 greater than  and defect address FCA  less than 8:1 greater than  from program circuit 33a to generate defect determination signal SCE. To be concrete, when each bit of even-numbered address CAE  less than 8:1 greater than  and each bit of defect address FCA  less than 8:1 greater than  all coincide with each other, defect determination signal SCE is set to H level. In response to the setting, spare column decoder 4a is activated and data is read out from a redundant bit line corresponding to a redundant memory cell column.
Consideration is given to a determination operation of redundancy determining circuits 35a and 35b of an even-numbered bit line and an odd-numbered bit line, respectively, and in a case of odd-numbered address CAO corresponding to an odd bit line, a bit address of column address CA is used as is in redundancy determining circuit 35a, while in a case of even-numbered address CAE, even-numbered address CAE is a conversion of column address CA on the basis of even-numbered address buffer 40 in a prescribed condition; therefore, a determination operation of redundancy determining circuit 35b of even-numbered address CAE lags by a conversion time of even-numbered address buffer 40. In company with the delay, a column select operation also delays; therefore, a problem arises of no possibility of a high speed operation in a double data rate scheme in which data reading is performed in synchronization with clock signal.
It is an object of the present invention to provide a synchronous semiconductor memory device canceling a delay in a determination operation accompanying a conversion operation of an even-numbered address buffer to perform high speed data reading and so on.
A semiconductor memory device according to an aspect of the present invention includes: plural memory cells arranged in a matrix; redundant memory cells for being substituted for a defective memory cell among the plural memory cells for the sake of saving; an address conversion circuit; a defect address conversion circuit; an address comparison circuit; and a select circuit. The address conversion circuit receives an address signal of L bits (where L is an integer of 2 or more) for selecting plural memory cells to apply a prescribed conversion operation to a bit or bits of part of the L bits when necessary. The defect address conversion circuit receives a defect address signal of L bits, stored in advance, and corresponding to the defective memory cell to apply an inverse conversion operation, exercised by inverting a relationship between an input and output in the prescribed conversion operation applied by the address conversion circuit, to a bit or bits of part of the defect address signal. The address comparison circuit receives an address signal before passage through the address conversion circuit and a defect address signal after passage through the defect address conversion circuit to compare them with each other. The select circuit gets access to one of a memory cell corresponding to an address signal after passage through the address conversion circuit and a redundant memory cell according to a result of comparison in the address comparison circuit.
A main advantage of the present invention is that an address signal before passage through the address conversion circuit and a defect address signal after passage through the defect address conversion circuit are compared with each other in the address comparison circuit, thereby enabling access to a redundant memory cell according to a result of the comparison. That is, since no necessity arises for use of an address signal after passage through the address conversion circuit in the address comparison circuit, suppression can be achieved of a delay time accompanying passage through the address conversion circuit in the address conversion circuit. Accordingly, high speed access to a memory cell and a redundant memory cell can be obtained, thereby enabling times required for data reading and writing to be shortened.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.